Efficient hardware for the Tate pairing calculation in characteristic three

Title	Efficient hardware for the Tate pairing calculation in characteristic three
Publication Type	Conference Paper
Year of Publication	2005
Authors	Kerins, T., W. MARNANE, E. POPOVICI, and P. S. L. M. BARRETO
Conference Name	7th International Workshop - Cryptographic Hardware and Embedded Systems -- CHES'2005
Date Published	September, 2005
Publisher	Lecture Notes in Computer Science - Springer Berlin / Heidelberg
Conference Location	Edinburgh, UK
ISBN Number	0302-9743 (Print) 1611-3349 (Online)
Abstract	In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF(3^6m) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF(3^m). Using this approach, an architecture for the hardware implementation of the Tate pairing calculation based on a modified Duursma-Lee algorithm is proposed.
URL	http://www.springerlink.com/content/3841kkkpkmmxlnnd/?p=31d080e6b9d1470ca8916c2bc5ce71bd&pi=29
DOI	10.1007/11545262_30