<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Ronan, Robert</style></author><author><style face="normal" font="default" size="100%">Heigeartaigh, Colm O</style></author><author><style face="normal" font="default" size="100%">Murphy, Colin</style></author><author><style face="normal" font="default" size="100%">Kerins, Tim</style></author><author><style face="normal" font="default" size="100%">BARRETO, Paulo S. L. M.</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A Reconfigurable Processor for the Cryptographic nT Pairing in Characteristic 3</style></title><secondary-title><style face="normal" font="default" size="100%">Fourth International Conference on Information Technology (ITNG'07) - Fourth International Conference on Information Technology (ITNG'07)</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2007</style></year><pub-dates><date><style  face="normal" font="default" size="100%">16 de abril 2007</style></date></pub-dates></dates><urls><web-urls><url><style face="normal" font="default" size="100%">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4151653&amp;tag=1</style></url></web-urls></urls><publisher><style face="normal" font="default" size="100%">IEEE</style></publisher><pub-location><style face="normal" font="default" size="100%">Las Vegas, NV, USA</style></pub-location><pages><style face="normal" font="default" size="100%">11 - 16</style></pages><isbn><style face="normal" font="default" size="100%">0-7695-2776-0</style></isbn><abstract><style face="normal" font="default" size="100%">&lt;p&gt;Recently, there have been many proposals for secure and novel cryptographic protocols that are built on bilinear pairings. The eta &lt;sub&gt;T&lt;/sub&gt; pairing is one such pairing and is closely related to the Tate pairing. In this paper we consider the efficient hardware implementation of this pairing in characteristic 3. All characteristic 3 operations required to compute the pairing are outlined in detail. An efficient, flexible and reconfigurable processor for the eta&lt;sub&gt;T &lt;/sub&gt;pairing in characteristic 3 is presented and discussed. The processor can easily be tailored for a low area implementation, for a high throughput implementation, or for a balance between the two. Results are provided for various configurations of the processor when implemented over the field F&lt;sub&gt;397&lt;/sub&gt; on an FPGA&lt;/p&gt;</style></abstract></record></records></xml>