<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Kerins, T.</style></author><author><style face="normal" font="default" size="100%">Marnane, W.P.</style></author><author><style face="normal" font="default" size="100%">Popovici, E.M.</style></author><author><style face="normal" font="default" size="100%">BARRETO, Paulo S. L. M.</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Hardware accelerators for pairing based cryptosystems</style></title><secondary-title><style face="normal" font="default" size="100%">IEE Proceedings - Information Security</style></secondary-title><short-title><style face="normal" font="default" size="100%">IEE Proceedings - Information Security</style></short-title></titles><dates><year><style  face="normal" font="default" size="100%">2005</style></year><pub-dates><date><style  face="normal" font="default" size="100%">Oct. 2005 </style></date></pub-dates></dates><urls><web-urls><url><style face="normal" font="default" size="100%">http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&amp;arnumber=1541358</style></url></web-urls></urls><number><style face="normal" font="default" size="100%">1</style></number><volume><style face="normal" font="default" size="100%">152</style></volume><pages><style face="normal" font="default" size="100%">47</style></pages><abstract><style face="normal" font="default" size="100%">&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;Polynomial basis hardware architectures are described for the mathematical operations required in pairing based cryptosystems in characteristic &lt;/font&gt;&lt;/font&gt;&lt;/font&gt;&lt;font face=&quot;AdvTimes-i&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvTimes-i&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvTimes-i&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;p&lt;/font&gt;&lt;/font&gt;&lt;/font&gt;&lt;font face=&quot;AdvP4C4E74&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvP4C4E74&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvP4C4E74&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&amp;frac14;&lt;/font&gt;&lt;/font&gt;&lt;/font&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;3. In hardware, arithmetic operations in extension fields of GF(3&lt;/font&gt;&lt;/font&gt;&lt;/font&gt;&lt;font face=&quot;AdvTimes-i&quot; color=&quot;#292526&quot; size=&quot;1&quot;&gt;&lt;font face=&quot;AdvTimes-i&quot; color=&quot;#292526&quot; size=&quot;1&quot;&gt;&lt;font face=&quot;AdvTimes-i&quot; color=&quot;#292526&quot; size=&quot;1&quot;&gt;m&lt;/font&gt;&lt;/font&gt;&lt;/font&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;) can be parallelised, and this results in high performance dedicated processors for efficient Tate pairing calculation. The implementation aspects of two such hardware processors are discussed through prototyping over GF(3&lt;/font&gt;&lt;/font&gt;&lt;/font&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;1&quot;&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;1&quot;&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;1&quot;&gt;97&lt;/font&gt;&lt;/font&gt;&lt;/font&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;&lt;font face=&quot;AdvTimes&quot; color=&quot;#292526&quot; size=&quot;2&quot;&gt;) on the Xilinx Virtex2 and Virtex2Pro FPGA technologies.&lt;span id=&quot;1273063898527E&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;span id=&quot;1273063893999E&quot;&gt;&amp;nbsp;&lt;/span&gt;&lt;/font&gt;&lt;/font&gt;&lt;/font&gt;&lt;/p&gt;</style></abstract><issue><style face="normal" font="default" size="100%">1</style></issue></record></records></xml>